Semiconductor Package

ABSTRACT

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

FIELD OF THE INVENTION

The invention relates to semiconductor packages. More particularly, itrelates to wafer level chip scale packages (WLCSP).

BACKGROUND OF THE INVENTION

In the semiconductor industry, the integration density within a die isgrowing rapidly. A die can include a huge amount of active and passiveelectronic devices so that a lot of functions can be performed withinthe die. The electronic devices are formed by semiconductormanufacturing processes on a silicon wafer. After the manufacturingprocesses of the electronic devices are finished, the wafer can beseparated into many dies. Each die may then go through packagingprocesses so that a protection package is formed outside the die. Thepackage for a die can also be an interface for connections between thedie and a printed circuit board. Typical applications for integratedcircuits include mobile phone systems, television systems, personalcomputer systems, and networking systems.

Many types of package have been developed, such as dual in-line pinpackage (DIP), quad flat package (QFP), ball grid array (BGA), and waferlevel chip scale package (WLCSP). A DIP has connection pins on twoparallel sides. DIPs usually use through-hole-mounting or sockets to beplaced on printed circuit boards. DIPs usually comprise insulatingmaterials filled around a metal lead frame.

A QFP usually has wing-like leads extending from four sides of thepackage. A QFP has connections only from the peripheral area of thepackage, so its pin count is limited. A BGA can use a whole surface toform an array of connections so that it can provide higher ball count.The length between the array of connections and the die is shorter,which is better for high speed signal transmission. A WLCSP can have apackaged device which is nearly the same size of a die. A WLCSP isgenerally smaller than a BGA package.

SUMMARY OF THE INVENTION

One objective of the invention is to provide a semiconductor devicehaving a metal post with wider connection areas at both ends.

Another objective of the invention is to provide a semiconductor devicehaving a metal post capable of connecting to a DRAM module through amolding material.

Still another objective of the invention is to provide a semiconductordevice having a metal post with a wider connection area at an endconnecting to a redistribution structure.

According to one aspect of the invention, a semiconductor device isdisclosed. The semiconductor device comprises a redistributionstructure, a processor die, and a metal post. The processor die has anactive side and a back side. The active side faces a first direction.The active side of the processor die is connected to the redistributionstructure.

The metal post has a first end, a second end and a waist. The metal postis connected to the redistribution structure at the first end. The firstend faces the first direction. The first end has a first width. Thesecond end has a second width. The waist has a waist width. The firstwidth is greater than the waist width. The second width is greater thanthe waist width. The metal post has a side surface. The side surface isinwardly curved.

According to another aspect of the invention, a semiconductor device isdisclosed. The semiconductor device comprises a redistributionstructure, a processor die, and a metal post. The processor die has anactive side and a back side. The active side faces a first direction.The active side of the processor die is connected to the redistributionstructure.

The metal post has a first end, a second end and a waist. The metal postis connected to the redistribution structure at the first end. The firstend faces the first direction. The first end has a first width. Thesecond end has a second width. The waist has a waist width. The firstwidth is greater than the second width. The second width is greater thanthe waist width. The metal post has a side surface. The side surface isinwardly curved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an embodiment of a semiconductor device;

FIG. 2 shows a cross-sectional view of a redistribution structure;

FIG. 3 shows a cross-sectional view of another redistribution structure;

FIG. 4 shows an embodiment of a semiconductor device;

FIG. 5 shows a cross-sectional view of a connection structure;

FIG. 6 shows a cross-sectional view of another connection structure;

FIG. 7 shows a cross-sectional view and a top view of a via;

FIG. 8 shows a cross-sectional view and a top view of two vias;

FIG. 9 shows a cross-sectional view of two vias;

FIG. 10 shows a cross-sectional view and a top view of three vias;

FIG. 11 shows a cross-sectional view of via zones and top views of twovias;

FIG. 12 shows a cross-sectional view of via zones and top views of fourvias;

FIG. 13 shows a cross-sectional view of via zones and top views of threevias;

FIG. 14 shows a top view of five vias;

FIG. 15 shows a top view of five vias;

FIG. 16 shows a top view of a plurality of vias;

FIG. 17 shows a top view of a plurality of vias;

FIG. 18 shows a cross-sectional view of a connection structure;

FIG. 19 shows a semiconductor device with a DRAM module;

FIG. 20 shows a part of a redistribution structure;

FIG. 21 shows a side view of a semiconductor device;

FIG. 22 shows an example of a connection structure between a die and aredistribution structure;

FIG. 23 shows another example of a connection structure between a dieand a redistribution structure;

FIG. 24 shows another example of a connection structure between a dieand a redistribution structure;

FIG. 25 shows another example of a connection structure between a dieand a redistribution structure;

FIG. 26 shows another example of a connection structure between a dieand a redistribution structure;

FIG. 27 shows another example of a connection structure between a dieand a redistribution structure;

FIG. 28 shows a part of a redistribution structure;

FIG. 29 shows an example of a metal layer in a redistribution structure;

FIG. 30 shows another example of a metal layer in a redistributionstructure;

FIG. 31 shows another example of a metal layer in a redistributionstructure;

FIG. 32 shows a top view of a semiconductor device;

FIG. 33 shows a semiconductor package with a DRAM module;

FIG. 34 shows a detailed redistribution structure;

FIG. 35 shows an example of a metal post;

FIG. 36 shows another example of a metal post;

FIG. 37 shows a solder bump at an end of a metal post;

FIG. 38 shows a solder bump at an end of a metal post;

FIG. 39 shows a semiconductor device;

FIG. 40 shows a semiconductor device;

FIG. 41 shows a detailed redistribution structure;

FIG. 42 shows a top view and a cross-sectional view of a conductive via;

FIG. 43 shows a top view and a cross-sectional view of a conductive via;

FIG. 44 shows cross-sectional views of conductive vias;

FIG. 45 shows cross-sectional views of conductive vias;

FIG. 46 shows a top view of a conductive via;

FIG. 47 shows a top view of a conductive via;

FIG. 48 shows a top view of a conductive via;

FIG. 49 shows a top view of a conductive via; and

FIG. 50 shows a top view of a conductive via.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows an embodiment of a semiconductor device. FIG. 2 shows across-sectional view of a redistribution structure. FIG. 3 shows across-sectional view of another redistribution structure. FIG. 4 showsan embodiment of a semiconductor device. FIG. 5 shows a cross-sectionalview of a connection structure. FIG. 6 shows a cross-sectional view ofanother connection structure. FIG. 7 shows a cross-sectional view and atop view of a via. FIG. 8 shows a cross-sectional view and a top view oftwo vias. FIG. 9 shows a cross-sectional view of two vias.

FIG. 10 shows a cross-sectional view and a top view of three vias. FIG.11 shows a cross-sectional view of via zones and top views of two vias.FIG. 12 shows a cross-sectional view of via zones and top views of fourvias. FIG. 13 shows a cross-sectional view of via zones and top views ofthree vias. FIG. 14 shows a top view of five vias. FIG. 15 shows a topview of five vias. FIG. 16 shows a top view of a plurality of vias. FIG.17 shows a top view of a plurality of vias. FIG. 18 shows across-sectional view of a connection structure.

According to an embodiment, with reference to FIG. 1 and FIG. 5 , aconnection structure 500 is disclosed. The connection structure 500comprises a conductive unit 205, a solder bump 206, a first insulatinglayer 501, a second insulating layer 502, a third insulating layer 503,and a plurality of vias 1602. The conductive unit 205 has a rim 509. Theconductive unit 205 comprises a flange 506, a slanting side wall 507,and a base 508. The solder bump 206 is located on the conductive unit205. The solder bump 206 is in direct contact with the conductive unit205. The rim 509 is a curve (viewed from the top of the conductive unit205) where the flange 506 meets the slanting side wall 507.

The first insulating layer 501 is located under the flange 506. Thesecond insulating layer 502 is located under the base 508 of theconductive unit 205. The third insulating layer 503 is located under thesecond insulating layer 502. The third insulating layer 503 has a viazone 512. The plurality of vias 1602 are located in the via zone 512.The via zone 512 is within a vertical projection 513 of the conductiveunit 205.

The solder bump includes without limitation both lead-based andlead-free solders, such as Pb-Sn compositions for lead-based solder, andlead-free solders including tin, copper, and silver, or “SAC”compositions, and other eutectics that have a common melting point andform conductive solder connections in electrical applications. In someembodiments, the conductive unit 250 includes under bump metal (UBM). Insome embodiments, UBM structures include one or more metallic layers,such as layers of titanium and of copper. The UBM can be formed bydeposition.

In some embodiments, with reference to FIG. 1 , FIG. 5 , and FIG. 16 ,the via zone 512 is a second via zone 512. The second insulating layer502 has a first via zone 511. The connection structure 500 comprises aplurality of first vias 1601 located in the first via zone 511. Theplurality of first vias 1601 are not located beneath the base 508 of theconductive unit 205. In some embodiments, the via zone 512 is within avertical projection of the rim 509.

In some embodiments, most part of the first via zone 511 is under thebase 508 and the slanting side wall 507. That is, most part of the firstvia zone 511 is under a vertical projection 515 of the base 506 and theslanting side wall 507. A via zone is where vias are allowed to beimplemented. In some embodiments, vias are not allowed to be implementedoutside a via zone. In some embodiments, the vertical projection 515 isa ring shape from a top view.

With reference to FIG. 5 and FIG. 6 , a via zone 516 is twice as largeas the first via zone 511 from the cross sectional view. It means thatthe via zone 516 has more space for implementing vias. A via zone 517that is the same as the via zone 516 is formed in a fourth insulatinglayer 504. That is, the via zone 517 allows the same number of vias asthe via zone 516 to implement therein. In some embodiments, the numberof vias in the via zone 516 is the same as the number of vias in the viazone 507. In some embodiments, each of the vias in the via zone 516 hasa corresponding via in the via zone 517. In some embodiments, thecorresponding vias in the via zone 516 and the via zone 517 are alignedvertically.

The insulating layers 501, 502, 503, and 504 can be polyimide, BCB(Benzocyclobutene), PBO (PolyBenzobisOxazole), or other material havingsimilar insulating properties.

In some embodiments, the redistribution structure 102 further has a viazone 518. The via zone 518 is the same size as the via zone 512 andallows the same number of vias to be implemented. That is, when the viazone 512 can allow 4 vias to implement, the via zone 518 can also allow4 vias to implement. In some embodiments, each via in the via zone 512has a corresponding via in the via zone 518. In some embodiments, thecorresponding vias in the via zone 512 and the via zone 518 are alignedvertically.

With reference to FIG. 7 , a via 701 comprises a flange 704, a slantingside wall 705, and a base 706. The via 701's corresponding top view canbe represented by two rings. The inner ring 703 represents a top view ofa rim 702. The rim 702 is a curve where a flange 704 meets the slantingside wall 705. The outer ring 707 is a top view of a circular edge ofthe via 701.

In some embodiments, with reference to FIG. 8 , the plurality of vias1602 comprises a first via 801 and a second via 802. The first via 801comprises a first via flange 804, a first via slanting wall 803, and afirst via base 807. The second via 802 comprises a second via flange805, a second via slanting wall 806, and a second via base 808. Thefirst via flange 804 and the second via flange 805 have an overlappedarea 809. In some embodiments, the first via flange 804 is an annularflange with a uniform width. In some embodiments, the first via flange804 is an annular flange with a nonuniform width.

In some embodiments, the first via flange 804 has a first width 810 at afirst location 813 and a second width 812 at a second location 814. Thesecond location 814 is closer to a central point 815 of the overlappedarea 809 than the first location 813. In some embodiments, the secondvia flange 805 is an annular flange with a uniform width. In someembodiments, the second via flange 805 is an annular flange with anonuniform width. In some embodiments, the second via flange 805 has afirst width 811 at a first location 816 and a second width 817 at asecond location 818. The second location 818 is closer to a centralpoint 815 of the overlapped area 809 than the first location 816.

According to another embodiment, with reference to FIG. 1 , FIG. 2 ,FIG. 4 , and FIG. 5 , a semiconductor device 100 is disclosed. Thesemiconductor device 100 comprises a die 101, a redistribution structure102, a printed circuit board 401, and a nonvolatile memory module 402.The die 101 has an active side 103 and a back side 104.

The redistribution structure 102 has a front surface 201 and a backsurface 202. The front surface 201 is connected to the active side 103of the die 101 through a set of metal pillars 204. The redistributionstructure 102 comprises a conductive unit 205, a first solder bump 206,a first insulating layer 501, a second insulating layer 502, a thirdinsulating layer 503, and a plurality of vias 1602. The conductive unit205 has a rim 509. The metal pillars 204 can be aluminum (Al), copper(Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or othersuitable electrically conductive material.

The conductive unit 205 comprises a flange 506, a slanting side wall507, and a base 508. The back surface 202 is a surface of the firstinsulating layer 501. The first solder bump 206 is located on theconductive unit 205. The first solder bump 206 is in direct contact withthe conductive unit 205. The first insulating layer 501 is located underthe flange 506. The second insulating layer 502 is located under thebase 508 of the conductive unit 205. The third insulating layer 503 islocated under the second insulating layer 502. The third insulatinglayer 503 has a via zone 512. The plurality of vias 1602 are located inthe via zone 512. The via zone 512 is within a vertical projection 513of the conductive unit 205.

The redistribution structure 102 is connected to the printed circuitboard 401 through the solder bumps 206. The nonvolatile memory module402 is connected to the printed circuit board 401 through a plurality ofsecond solder bumps 403. A DRAM (Dynamic Random Access Memory) module405 is connected to the redistribution structure 102 through a pluralityof third solder bumps 406 and a plurality of metal posts 107. The metalposts 107 can be formed by plating. The material for the metal post 107can be Cu, Al, W, Au, solder, or other suitable electrically conductivematerial.

In some embodiments, the metal posts 107 are connected to theredistribution structure 102 and the solder bumps 406. Electricalsignals can be transmitted between the redistribution structure 102 andthe DRAM module 405 through the metal posts 107. In some embodiments,the nonvolatile memory module 402 is a Flash memory module.

In some embodiments, an adhesive layer 106 is located on the back side104 of the die 101. A molding material 105 is filled between the die 101and the metal posts 107. The molding material 105 is in direct contactwith the redistribution structure 102. The adhesive layer 106 can be adie attach film (DAF), or the like. The molding material 105 can be apolymer composite material, such as epoxy resin with filler, epoxyacrylate with filler, or polymer with proper filler.

In some embodiments, with reference to FIG. 2 , the redistributionstructure 102 further comprises a fourth insulating layer 504 and afifth insulating layer 505. Metal traces 207 are formed on surfaces ofthe second insulating layer 502, the third insulating layer 503, thefourth insulating layer 504, and the fifth insulating layer 505 to formproper connections between vias. The metal traces 207 can be aluminum(Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), orother suitable electrically conductive material.

In some embodiments, with reference to FIG. 2 and FIG. 3 , theconductive unit 205 is not needed. The solder bump 206 is directlyconnected to the trace 207. In some embodiments, there are four or morethan four insulating layers in the redistribution structure 102. Thethickness of metal trace for each insulating layer can be different. Forexample, the thickness of metal trace in an upper insulating layer canbe greater than the thickness of metal trace in a lower insulatinglayer. The thickness difference between metal traces of adjacentinsulating layers can also be different. For example, a first thicknessdifference is defined as the difference between the thickness of metaltrace in the first insulating layer 501 and the thickness of metal tracein the second insulating layer 502. A second thickness difference isdefined as the difference between the thickness of metal trace in thesecond insulating layer 502 and the thickness of metal trace in thethird insulating layer 503, and so on. Then we can have a firstthickness difference, a second thickness difference, a third thicknessdifference, and so on, depending on the number of insulating layers. Insome embodiments, the first thickness difference, the second thicknessdifference, the third difference are substantially the same. In someembodiments, the first thickness difference is smaller than the thesecond thickness difference and the second thickness difference isgreater than the third thickness difference. That is, there can be amore significant thickness difference of metal traces between adjacentinsulating layers in the middle of the redistribution structure. Thiscase can have advantages. For example, using similar metal tracethickness in a first group of insulating layers and then changing intoanother metal trace thickness in a second group of insulating layers cansave the complexity of adjusting metal trace thickness for eachinsulating layer.

In some embodiments, the via zone 512 is a second via zone 512. Thesecond insulating layer 502 has a first via zone 511. With reference toFIG. 16 , the semiconductor device 100 further comprises a plurality offirst vias 1601 located in the first via zone 511. The plurality offirst vias 1601 are not located beneath the base 506 of the conductiveunit 205.

According to another embodiment, with reference to FIG. 1 , FIG. 5 , andFIG. 9 , a connection structure 500 comprises a conductive unit 205, asolder bump 206, a first insulating layer 501, a second insulating layer502, a third insulating layer 503, a first via 801, and a second via802. The conductive unit 205 has a rim 509. The conductive unit 205comprises a flange 506, a slanting side wall 507, and a base 508. Thesolder bump 206 is located on the conductive unit 205. The solder bump206 is in direct contact with the conductive unit 205.

The first insulating layer 501 is located under the flange 506. Thesecond insulating layer 502 is located under the base 508 of theconductive unit 205. The third insulating layer 503 is located under thesecond insulating layer 502.

The first via 801 has a first via rim 820. The first via rim 820 has afirst via rim diameter 822. The first via 801 has a first via bottomedge 818. The first via 801 is within a vertical projection of theconductive unit 205. The second via 802 has a second via rim 821. Thesecond via rim 821 has a second rim diameter 823. The second via 802 hasa second via bottom edge 819. The second via 802 is within the verticalprojection of the conductive unit 205. A bottom edge distance 824 is adistance between the first via bottom edge 818 and the second via bottomedge 819. The first rim diameter 822 is greater than the bottom edgedistance 824.

With reference to FIG. 5 , FIG. 6 , and FIG. 10 , in some embodiments,three vias 1001, 1002, and 1003 are implemented within the via zone 511.The three vias 1001, 1002, and 1003 are within the vertical projectionof the conductive unit 205. In some embodiments, the three vias 1001,1002, and 1003 are located within the vertical projection of the rim509. The via 1001 has a flange 1004. The via 1002 has a flange 1005. Thevia 1003 has a flange 1006. The flange 1004 and the flange 1005 have anoverlapped area 1007. The flange 1005 and the flange 1006 have anoverlapped area 1008.

With the overlapped areas 1007 and 1008, the three vias 1001, 1002, and1003 are located more closely. The closely located vias 1001, 1002, 1003have the function of reducing stress. For the via 1002, the existence ofthe via 1001 and the via 1003 makes a surface 1010 rugged on both sidesof the via 1001, so that the stress applied onto a base 1009 of the via1002 is reduced. The surface 1010 is a surface formed by the vias 1001,1003, and traces 207 on an insulating layer 1013. Similarly, the stressapplied onto a base 1011 of the via 1001 is reduced. The stress appliedonto a base 1012 of the via 1003 is also reduced.

In some embodiments, with reference to FIG. 16 , the connectionstructure 500 further comprises a plurality of vias 1601 located withinthe second insulating layer 502. No via of the second insulating layer502 is located beneath the base 508 of the conductive unit 205. In someembodiments, the first via 801 and the second via 802 are within avertical projection of the rim 509.

In some embodiments, with reference to FIG. 8 , the first via 801comprises a first via flange 804, a first via slanting wall 803, and afirst via base 807. The second via 802 comprises a second via flange805, a second via slanting wall 806, and a second via base 808. Thefirst via flange 804 and the second via flange 805 have an overlappedarea 809.

In some embodiments, the first via flange 804 is an annular flange witha uniform width. In some embodiments, the first via flange 804 is anannular flange with a nonuniform width. In some embodiments, the firstvia flange 804 has a first width 810 at a first location 813 and asecond width 812 at a second location 814. The second location 814 iscloser to a central point 815 of the overlapped area 809 than the firstlocation 813.

According to another embodiment, with reference to FIG. 1 , FIG. 4 ,FIG. 5 , and FIG. 9 , a semiconductor device 100 comprises a die 101, aredistribution structure 102, a printed circuit board 401, a nonvolatilememory module 402, and a DRAM module 405.

The die 101 has an active side 103 and a back side 104. Theredistribution structure 102 has a front surface 201 and a back surface202. The front surface 201 is connected to the active side 103 of thedie 101 through a set of metal pillars 204. The redistribution structure102 comprises a conductive unit 205, a solder bump 206, a firstinsulating layer 501, a second insulating layer 502, a third insulatinglayer 503, a first via 801, and a second via 802. The back surface 202is a surface of the first insulating layer 501.

The conductive unit 205 has a rim 509. The conductive unit 205 comprisesa flange 506, a slanting side wall 507, and a base 508. The solder bump206 is located on the conductive unit 205. The solder bump 206 is indirect contact with the conductive unit 205. The first insulating layer501 is located under the flange 506. The second insulating layer 502 islocated under the base 508 of the conductive unit 205. The thirdinsulating layer 503 is located under the second insulating layer 502.

With reference to FIG. 5 and FIG. 9 , the first via 801 has a first viarim 820. The first via 801 and the second via 802 are implemented in thevia zone 512. The first via rim 820 has a first via rim diameter 822.The first via 801 has a first via bottom edge 818. The first via 801 iswithin a vertical projection of the conductive unit 205. The second via802 has a second via rim 821. The second via rim 821 has a second rimdiameter 823. The second via 802 has a second via bottom edge 819. Thesecond via 802 is within the vertical projection of the conductive unit205. A bottom edge distance 824 is a distance between the first viabottom edge 818 and the second via bottom edge 819. The first rimdiameter 822 is greater than the bottom edge distance 824.

With reference to FIG. 4 , the redistribution structure 102 is connectedto the printed circuit board 401 through the solder bumps 206. Thenonvolatile memory module 402 is connected to the printed circuit board401 through a plurality of second solder bumps 403. With reference toFIG. 1 and FIG. 4 , the DRAM module 405 is connected to theredistribution structure 102 through a plurality of third solder bumps406 and a plurality of metal posts 107. In some embodiments, no via ofthe second insulating layer 502 is located beneath the base 508 of theconductive unit 205.

According to another embodiment, with reference to FIG. 1 , FIG. 5 , andFIG. 9 , and FIG. 16 , a connection structure 500 comprises a conductiveunit 205, a solder bump 206, a first insulating layer 501, a secondinsulating layer 502, a third insulating layer 503, a first via 801, asecond via 802, a third via 825, and a fourth via 826.

The conductive unit 205 has a rim 509. The conductive unit 205 comprisesa flange 506, a slanting side wall 507, and a base 508. The solder bump206 is located on the conductive unit 205. The solder bump 206 is indirect contact with the conductive unit 205. The first insulating layer501 is located under the flange 506. The second insulating layer 502 islocated under the base 508 of the conductive unit 205. The thirdinsulating layer 503 is located under the second insulating layer 502.

The first via 801 is located in the third insulating layer 503. Morethan half of the first via 801 is within a vertical projection of therim 509 of the conductive unit 205. The second via 802 is located in thethird insulating layer 503. More than half of the second via 802 iswithin the vertical projection of the rim 509 of the conductive unit205.

The third via 825 is located in the second insulating layer 502. Morethan half of the third via 825 is within a vertical projection of theflange 506 and the slanting side wall 507 of the conductive unit 205.The fourth via 826 is located in the second insulating layer 502. Morethan half of the fourth via 826 is within the vertical projection of theflange 506 and the slanting side wall 507 of the conductive unit 205.

In some embodiments, the first via 801, the second via 802, the thirdvia 825, and the fourth via 826 are symmetric with respect to a firstaxis 827. In some embodiments, the first via 801, the second via 802,the third via 825, and the fourth via 826 are lined up along a secondaxis 828. In some embodiments, the connection structure 500 furthercomprises a fifth via 830 and a sixth via 831. More than half of thefifth via 830 is within the vertical projection of the flange 506 andthe slanting side wall 507 of the conductive unit 205. More than half ofthe sixth via 831 is within the vertical projection of the flange 506and the slanting side wall 507. The vias 801, 802, 825, 826, 830, and831 can be aluminum, copper, tungsten, gold, silver, or other suitableelectrically conductive material. The method of forming the metal viascan be plating.

With reference to FIG. 5 and FIG. 16 , in some embodiments, a pluralityof vias are implemented in a via zone 519 of an insulating layer 504.The insulating layer 504 is located beneath the insulating layer 503. Insome embodiments, the vias in the via zone 519 are corresponding to thevias in the via zone 511. In some embodiments, the vias in the via zone511 are vertically aligned with the vias in the via zone 519. In someembodiments, the number of vias in the via zone 511 is the same as thenumber of vias in the via zone 519.

In some embodiments, the vias in the via zone 519 have the samearrangement as the vias in the via zone 511. In some embodiments, athickness of bases of vias in the via zone 519 is smaller than athickness of bases of vias in the via zone 511. In some embodiments,with reference to FIG. 2 and FIG. 5 , the conductive unit 205, all viasin the via zone 511, all vias in the via zone 512, all vias in the viazone 519 are electrically connected through metal traces 207 in eachinsulating layer.

In some embodiments, with reference to FIG. 16 , the third via 825, thefourth via 826, the fifth via 830, and the sixth via 831 are symmetricwith respect to a central point 829. In some embodiments, with referenceto FIG. 8 , the first via 801 comprises a first via flange 804, a firstvia slanting wall 803, and a first via base 807. The second via 802comprises a second via flange 805, a second via slanting wall 806, and asecond via base 808, and the first via flange 804 and the second viaflange 805 have an overlapped area 809.

In some embodiments, the via 801 and the via 802 are implemented in theinsulating layer 503. The via 825 and the via 826 are implemented in theinsulating layer 502. With reference to FIG. 8 and FIG. 16 , the via 830and the via 831 are implemented in the insulating layer 502. The viasbelonging to two adjacent layers are not aligned vertically. That is,the vias belonging to two adjacent layers are shifted with respect toeach other. In some embodiments, the via 801, the via 802, the via 825,the via 826, the via 830, the via 831, and the conductive unit 205 areall electrically connected through metal traces 207.

In some embodiments, the first via 801 comprises a first via flange 804,a first via slanting wall 803, and a first via base 807. The second via802 comprises a second via flange 805, a second via slanting wall 806,and a second via base 808. With reference to FIG. 11 , a first edge 832of the first via flange 804 touches a second edge 833 of the second viaflange 805.

With reference to FIG. 9 and FIG. 11 , the via 801 and the via 802 arewithin the via zone 512. In some embodiments, the edge 832 does nottouch the edge 833. A distance between the edge 832 and the edge 833 issmaller than the diameter of the rim 820 of the via 801. The distancebetween the edge 832 and the edge 833 is smaller than the diameter ofthe rim 821 of the via 802. In some embodiments, the edge 832 touchesthe edge 833 at one point. In some embodiments, the flange of the via801 is overlapped with the flange of the via 802 and an overlapped area809 is formed.

Placing the via 801 and the via 802 closely helps to reduce the stressapplied on the base of the via 801 and on the base of the via 802. Forthe via 801, the adjacent via 802 forms a rugged metal surface on oneside. It helps to reduce the stress transmitted from that side. For thevia 802, the adjacent via 801 forms a rugged metal surface on one side.It helps to reduce the stress transmitted from that side. Placing two ormore vias under the conductive unit 205 helps to increase conductivityfrom the conductive unit 205 to the lower vias and at the same timehelps to reduce stress.

With reference to FIG. 12 , in some embodiments, two vias 1201 and 1202are located within the left side via zone 516. Two other vias 1203 and1204 are located within the right side via zone 516. The via zone 516forms a ring shape from a top view. The via zone 512 forms a circleshape from a top view. In some embodiments, the via 1201 and the via1202 are separated from a distance smaller than a diameter of a rim ofthe via 1201. The distance is also smaller than a diameter of the rim ofthe via 1202. In some embodiments, the via 1201 touches the via 1202 atone point. In some embodiments, the via 1201 and the via 1202 have anoverlapped area 1205.

With reference to FIG. 13 , in some embodiments, three vias 1301, 1302,and 1303 are implemented within the via zone 512. In some embodiments,the via 1301 touches the via 1302 at one point. The via 1302 touches thevia 1303 at one point. In some embodiments, the via 1301 and the via1302 have an overlapped flange area 1304. The via 1302 and the via 1303have an overlapped flange area 1305.

With reference to FIG. 5 and FIG. 14 , in some embodiments, five vias1401 are implemented within a vertical projection 1402 of the rim 509 ofthe conductive unit 205. In some embodiments, three of the vias 1401 areimplemented along an axis 1404. In some embodiments, three of the vias1401 are implemented along an axis 1405. In some embodiments, all thevias 1401 are about the same size. In some embodiments, each of the vias1401 has an overlapped flange area with an adjacent via 1401.

With reference to FIG. 5 and FIG. 15 , in some embodiments, five vias1501 are implemented within a vertical projection 1502 of the rim 509 ofthe conductive unit 205. In some embodiments, three of the vias 1501 areimplemented along an axis 1504. In some embodiments, three of the vias1501 are implemented along an axis 1505. In some embodiments, all thevias 1501 are about the same size. In some embodiments, each of the vias1501 touches an adjacent via 1501 at one point.

With reference to FIG. 5 and FIG. 16 , the via 801 and the via 802 arewithin a vertical projection 1603 of the rim 509. In some embodiments, asmall portion of the via 801 is outside the vertical projection 1603 ofthe rim 509 and a large portion of the via 801 is within the verticalprojection 1603. In some embodiments, a small portion of the via 802 isoutside the vertical projection 1603 of the rim 509 and a large portionof the via 802 is within the vertical projection 1603. In someembodiments, the via 801, the via 802, the via 825, and the via 826 areimplemented along an axis 828. In some embodiments, the via 830 and thevia 831 are implemented along an axis 827.

With reference to Fig, 5 and FIG. 17 , in some embodiments, the via 801and the via 802 are located within a vertical projection 1701 of the rim509. The via 801 and the via 802 have an overlapped flange area 1702. Insome embodiments, a plurality of vias 1703 are implemented within avertical projection 1704 of the conductive unit 205.

According to another embodiment, with reference to FIG. 1 , FIG. 4 ,FIG. 5 , and FIG. 9 , and FIG. 16 , a semiconductor device 100 comprisesa die 101, a redistribution structure 102, a printed circuit board 401,a nonvolatile memory module 402, and a DRAM module 405.

The die 101 has an active side 103 and a back side 104. Theredistribution structure 102 has a front surface 201 and a back surface202. The front surface 201 is connected to the active side 103 of thedie 101 through a set of metal pillars 204. The redistribution structure102 comprises a conductive unit 205, a solder bump 206, a firstinsulating layer 501, a second insulating layer 502, a third insulatinglayer 503, a first via 801, a second via 802, a third via 825, and afourth via 826. The conductive unit 205 has a rim 509. The conductiveunit 205 comprises a flange 506, a slanting side wall 507, and a base508.

The solder bump 206 is located on the conductive unit 205. The solderbump 206 is in direct contact with the conductive unit 205. The firstinsulating layer 501 is located under the flange 506. The secondinsulating layer 502 is located under the base 508 of the conductiveunit 205. The third insulating layer 503 is located under the secondinsulating layer 502. The first via 801 is located in the thirdinsulating layer 503.

More than half of the first via 801 is within a vertical projection ofthe rim 509 of the conductive unit 205. The second via 802 is located inthe third insulating layer 503. More than half of the second via 802 iswithin the vertical projection of the rim 509 of the conductive unit205. The third via 825 is located in the second insulating layer 502.More than half of the third via 825 is within a vertical projection ofthe flange 506 and the slanting side wall 507 of the conductive unit205. The fourth via 826 is located in the second insulating layer 502.More than half of the fourth via 826 is within the vertical projectionof the flange 506 and the slanting side wall 507 of the conductive unit205.

The redistribution structure 102 is connected to the printed circuitboard 401 through the solder bump 206. The nonvolatile memory module 402is connected to the printed circuit board 401 through a plurality ofsecond solder bumps 403. The DRAM module 405 is connected to theredistribution structure 102 through a plurality of third solder bumps406 and a plurality of metal posts 107. In some embodiments, the firstvia 801, the second via 802, the third via 825, and the fourth via 826are symmetric with respect to a first axis 827.

With reference to FIG. 5 and FIG. 18 , a via 1801, a via 1802, and a via1803 are implemented within a vertical projection of the conductive unit205. A metal layer 1804 is implemented beneath the conductive unit 205.The metal layer 1804 is in direct contact with the base of theconductive unit 205. In some embodiments, the metal layer 1804 has anarea that is about the same size of the base of the conductive unit 205.

In some embodiments, the metal layer 1804 has an area that is largerthan the size of the base of the conductive unit 205. The area of themetal layer 1804 is just beneath the base of the conductive unit 205 sothat it provides good and full contact with the base of the conductiveunit 205. In some embodiments, no via is implemented in a zone 1805. Thezone 1805 is beneath the base of the conductive unit 205. In someembodiments, the metal layer 1804 is connected to the metal trace 207 sothat the metal layer 1804, the metal trace 207, the via 1801, the via1802, and the via 1803 are all electrically connected. In someembodiments, a metal post 1806 is located on top of the conductive unit205. In some embodiments, the metal post 1806 is replaced by a solderbump.

One objective of the embodiments is to provide a connection structurethat can help to reduce stress in a semiconductor package. Anotherobjective of the embodiments is to provide arrangements of vias below aconductive unit of a redistribution structure so that a betterconductivity is achieved. Still another objective of the embodiments isto provide a connection structure that is symmetric with respect to acentral point so that a balance of stress is achieved.

With reference to FIG. 19 and FIG. 20 , according to an embodiment, asemiconductor device 1900 is disclosed. The semiconductor device 1900comprises a die 1901, a redistribution structure 1902, a plurality ofconductive posts 1903, a DRAM module 1904, and a plurality of solderbumps 1905. The die 1901 has an active side 1906 and a back side 1907.The redistribution structure 1902 has a front surface 1908 and a backsurface 1909. The redistribution structure 1902 is connected to the die1901 through a plurality of conductive pillars 2001.

In some embodiments, the redistribution structure 1902 has a pluralityof sublayers 2002. The sublayers 2002 are insulating layers. Each of thesublayers 2002 comprises metal traces 2003 and vias 2004. Electricalsignals and power/ground levels are connected through the metal traces2003 and the vias 2004. In some embodiments, the redistributionstructure 1902 comprises a plurality of conductive units 2005 and aplurality of solder bumps 2006. Each solder bump 2006 is located on itscorresponding conductive unit 2005. In some embodiments, the conductiveunits are UBM (under-bump metallization) layers.

In some embodiments, the semiconductor device 1900 comprises an adhesivelayer 1910. The adhesive layer 1910 is a DAF (Die Attach Film). In someembodiments, the semiconductor device 1900 comprises a passive device1911 and a passive device 1912. The passive device 1911 is a capacitor.The passive device 1912 is a capacitor. In some embodiments, the passivedevice 1911 is an inductor. The passive device 1912 is an inductor. Insome embodiments, the passive device 1911 and the passive device 1912are within a vertical projection 1913 of the die 1901. From a top view,the projection 1913 is rectangular in shape because the die 1901 isrectangular.

In some embodiments, the passive device 1911 is connected to the backsurface 1909 of the redistribution structure 1902 through solder bumps2009. In some embodiments, the passive device 1911 is an IPD (IntegratedPassive Device). In some embodiments, the semiconductor device 1900comprises a passive device 1914 and a passive device 1915. The passivedevice 1914 is a capacitor. The passive device 1915 is a capacitor. Insome embodiments, the passive device 1914 is an inductor. The passivedevice 1915 is an inductor. In some embodiments, the passive device 1914and the passive device 1915 are within a vertical projection 1913 of thedie 1901.

In some embodiments, the semiconductor device 1900 comprises a passivedevice 1916 and a passive device 1917. In some embodiments, the passivedevice 1916 is a capacitor. The passive device 1917 is a capacitor. Insome embodiments, the passive device 1916 is an inductor. The passivedevice 1917 is an inductor. The passive device 1916 and the passivedevice 1917 are located on the front surface 1908 of the redistributionstructure 1902.

In some embodiments, the passive device 1916 and the passive device 1917are located beside the die 1901. In some embodiments, the passive device1916 and the passive device 1917 are located closer to the die 1901 thanany of the conductive posts 1903. In some embodiments, an underfillmaterial 1919 surrounds the solder bumps 1905. In some embodiments, aspace 1920 is formed under between the DRAM module 1904 and the adhesivelayer 1910. In some embodiments, the space 1920 is not filled by theunderfill material 1919. In some embodiments, the space 1920 is alsofilled with the underfill material 1919.

In some embodiments, the semiconductor device 1900 comprises a moldingmaterial 1918 filling a space between one of the conductive posts 1903and the die 1901. In some embodiments, the molding material 1918surrounds all conductive posts 1903. In some embodiments, thesemiconductor device 1900 comprises an insulating layer 2007 between thefront surface 1908 of the redistribution structure 1902 and the activeside 1906 of the die 1901. In some embodiments, the insulating layer2007 is a polymer layer. In some embodiments, the insulating layer 2007is a polyimide layer. In some embodiments, the insulating layer 2007 hasthe same material as the molding material 1918. In some embodiments, theinsulating layer 2007 surrounds each conductive pillar 2001 between theredistribution structure 1902 and the die 1901.

In some embodiments, the insulating layer 2007 does not provide forrouting of signal traces. That is, the insulating layer 2007 does nothave any redistribution function. No metal traces are formed on theinsulating layer 2007 for any routing purposes. With reference to FIG.20 and FIG. 24 , in some embodiments, no redistribution of metal tracesis provided below the front surface 1908 of the redistribution structure1902 and above the passivation layer 2401.

With reference to FIG. 22 , in some embodiments, the insulating layer2007 is located between the active side 1906 of the die 1901 and thefront surface 1908 of the redistribution structure 1902. In someembodiments, the insulating layer 2007 comprises polyimide. In someembodiments, the insulating layer 2007 is in direct contact with thefront surface 1908 of the redistribution structure 1902. In someembodiments, the insulating layer 2007 is in direct contact with theactive side 1906 of the die 1901.

With reference to FIG. 22 , the die 1901 has a die edge 2203. Theinsulating layer 2007 has an outer edge 2204. The die edge 2203 is notaligned with the outer edge 2204 of the insulating layer 2007vertically. There is a horizontal shift 2208 between the die edge 2203and the outer edge 2204 of the insulating layer 2007.

The reason for the horizontal shift 2208 is that during a dicing processof a wafer, the presence of a polymer insulating layer 2007 at scribelines of the wafer causes problems. If the insulating layer 2007 isformed on top of the scribe lines before a dicing process is performed,the insulating layer 2007 may not be easily cut during the dicingprocess because it has different chemical and physical characteristicscompared with the die 1901. In some cases, the insulating layer 2007 maybe peeled off by the dicing process and the structure of thesemiconductor device 1900 is destructed. Therefore, it is better to formthe insulating layer 2007 which keeps a distance from the edge 2203 ofthe die 1901. That is, the insulating layer 2007 is better not locatednear the scribe line area.

With reference to FIG. 22 , a recess 2205 is formed between theredistribution structure 1902 and the die 1901. In some embodiment, therecess 2205 is filled by the molding material 1918. In some embodiments,the adhesive layer 1910 has an edge 2206. The edge 2206 of the adhesivelayer 1910 is aligned vertically with the die edge 2203. In someembodiments, the molding material 1918 covers the die edge 2203 and theedge 2206 of the adhesive layer 1910. In some embodiments, the edge 2206of the adhesive layer is not vertically aligned with the die edge 2203.The edge 2206 of the adhesive layer 1910 creates a recess 2207 under thedie 1901. In some embodiments, the molding material 1918 filled therecess 2207.

With reference to FIG. 22 , the conductive pillars 2001 are surroundedby the insulating layer 2007. The conductive pillars 2001 are connectedto the vias 2004 of the redistribution structure 1902. The conductivepillars 2001 are also connected to the active side 1906 of the die 1901.The conductive pillars 2001 can be used to transmit electrical signalsbetween the redistribution structure 1902 and the die 1901. In someembodiments, the insulating layer 2002 uses the same material as thatused in the insulating layer 2007. In this case, the insulating layer2007 and the insulating layer 2002 have the same chemical and physicalcharacteristics so that there are no mismatches between the two layers.For example, the insulating layer 2007 and the insulating layer 2002have the same coefficient of thermal expansion so when environmenttemperature changes, there is no warpage caused by the changes.

With reference to FIG. 23 , in some embodiments, the insulating layer2007 is not in direct contact with the insulating layer 2002. A moldingmaterial 1918 is filled between the front surface 1908 of theredistribution structure 1902. The molding material 1918 surrounds upperportions of the conductive pillars 2001. The insulating layer 2007surrounds lower portions of the conductive pillars 2001.

With reference to FIG. 24 , the die 1901 comprises a passivation layer2401. The passivation layer 2401 has an edge 2402. The edge 2402 isaligned vertically with an edge 2403 of the die 1901. In someembodiments, the insulating layer 2007 has an outwardly curved surface2405. An upper surface 2407 of the passivation layer 2401 is in directcontact with the molding material 1918. In some embodiments, theinsulating layer 2007 has an edge 2408. The edge 2408 is not verticallyaligned with the edge 2402. There is a horizontal shift 2409 between theedge 2408 and the edge 2402.

With reference to FIG. 25 , in some embodiments, the insulating layer2007 has an outwardly curved surface 2501. The outwardly curved surface2501 is in direct contact with the molding material 1918. The outwardlycurved surface 2501 has an outermost point 2502. The outermost point2502 is not located on an interface between the insulating layer 2007and the passivation layer 2401. The outermost point 2502 is not locatedon an interface the insulating layer 2007 and the front surface 1908 ofthe redistribution structure 1902. The outermost point 2502 is notvertically aligned with the edge 2402 of the passivation layer 2401. Thefront surface 1908, the outwardly curved surface 2501, and thepassivation layer 2401 form a recess 2503.

In some embodiments, the recess 2503 is filled by the molding material1918. There is a horizontal shift 2504 between the outermost point 2502and the edge 2402 of the passivation layer 2401. In some embodiments, apart of an upper surface 2505 of the passivation layer 2401 is in directcontact with the molding material 1918.

With reference to FIG. 26 , in some embodiments, the insulating layer2007 has an inwardly curved surface 2601. The inwardly curved surface2601 has an outermost point 2602. The outermost point 2602 is located ona boundary between the inwardly curved surface 2601 and the uppersurface of the passivation layer 2401. There is a horizontal shift 2603between the outermost point 2602 and the edge 2402 of the passivationlayer 2401.

A recess 2604 is formed by the front surface 1908 of the redistributionstructure 1902, the inwardly curved surface 2601, and the passivationlayer 2401. In some embodiments, the recess 2604 is filled by themolding material 1918. In some embodiments, the outermost point 2602 islocated on a boundary between the inwardly curved surface 2601 and thefront surface 1908 of the redistribution structure. In this case, thereis a horizontal shift 2603 between the outermost point 2602 and thefront surface 1908 of the redistribution structure. In this case, a partof the upper surface 2505 of the passivation layer 2401 is in directcontact with the molding material 1918.

With reference to FIG. 27 , in some embodiments, the insulating layer2007 is not in direct contact with the front surface 1908 of theredistribution structure 1902. There is a gap 2701 between the frontsurface 1908 and the insulating layer 2007. In some embodiments, themolding material 1918 is filled in the gap 2701.

With reference to FIG. 28 , in some embodiments, the redistributionstructure 1902 comprises an insulating layer 2801, an insulating layer2802, an insulating layer 2803, and an insulating layer 2804. Theredistribution structure 1902 comprises a metal layer 2805, a metallayer 2806, and a metal layer 2807. The metal layer 2805 is on top ofthe insulating layer 2801. The metal layer 2806 is on top of theinsulating layer 2802. The metal layer 2807 is on top of the insulatinglayer 2803. A plurality of conductive units 2005 are formed on top ofthe insulating layer 2804. The metal layer 2805 is connected to theconductive pillars 2001 through vias 2004. The metal layer 2806 isconnected to the metal layer 2805 through vias 2004. The metal layer2807 is connected to the metal layer 2806 through vias 2004.

With reference to FIG. 28 , the metal layer 2805 comprises metal tracesthat transmit signals and metal traces for power and ground. The metallayer 2806 comprises metal traces that transmit signals and metal tracesfor power and ground. The metal layer 2807 comprises metal traces thattransmit signals and metal traces for power and ground. The metal layer2806, being between the metal layer 2805 and the metal layer 2807, has arelatively larger portion of metal traces designed for power and ground.That is, the metal layer 2806 has more power and ground areas comparedwith the metal layer 2805 and the metal layer 2807.

The metal layer 2805 has longer total length of signal routing metaltraces than the metal layer 2806. The metal layer 2807 has longer totallength of signal routing metal traces than the metal layer 2806. Themetal layer 2806 has longer power ground traces or metal areas than themetal layer 2805. The metal layer 2806 has longer power ground traces ormetal areas then the metal layer 2807. By placing large areas of powerand ground in the middle, the metal layer 2806 help maintain good signalintegrity for the signals transmitted by the metal layer 2805 and themetal layer 2807.

With reference to FIG. 28 and FIG. 29 , the metal layer 2806 has a powerground area 2901, a power ground area 2902, and a power ground area2903. In some embodiments, the power ground areas 2901 is formed by amesh type metal layer. The power ground area 2901 has a metal plane witha plurality of holes 2904 or slits 2904. A width of the holes 2904 isgenerally greater than a width of the metal traces 2905. The metaltraces 2905 from the boundary line of the power ground area 2901. Themetal traces 2905 also form inner lines among the plurality of holes2904. The power ground area 2901 is connected to a power level or aground level.

With reference to FIG. 28 and FIG. 29 , in some embodiments, the powerground area 2902 are formed by a plurality of metal traces 2905. Thereis no closed boundary formed by the metal traces 2905 for the powerground area 2902. The metal traces 2905 are metal islands connected tothe same power level or to the same ground level. In some embodiments,the metal layer 2806 comprises electrically isolated metal islandsimplemented between two power ground areas. For example, a plurality ofmetal islands 2908 are implemented between the power ground area 2901and the power ground area 2902. A plurality of metal islands 2908 areimplemented between the power ground area 2902 and a power ground area2903. The metal islands 2908 are electrically isolated so that they arenot connected vertically with another metal layer.

In some embodiments, a metal layer containing greater portion of powerground area can be placed between two metal layers having greaterportion of signal metal traces. For example, with reference to FIG. 28 ,the metal layer 2806 can have more ground area compared with the metallayer 2807. The metal layer 2806 can have more ground area compared withthe metal layer 2805. By placing a metal layer with significant groundarea between two metal layers with significant signal metal traces canhelp to prevent signal crosstalk and keep signal integrity.

With reference to FIG. 30 , in some embodiments, the metal layer 2806comprises a plurality of power ground areas. For example, one of thepower ground areas is formed by metal components 3001. One of the powerground areas is formed by metal components 3002. One of the power groundareas is formed by metal components 3003. One of the power ground areasis formed by metal components 3004. In some embodiments, each of themetal components 3001 is a polygon. In some embodiments, the metalcomponents 3001 are hexagons. In some embodiments, more than half of theinternal angles of each polygon are about 120 degrees. In someembodiments, the metal layer 2806 comprises a plurality of metal islands2908 between two power ground areas.

In some embodiments, not each metal component has the same size. Forexample, one of the metal components 3003 has twice the size ofneighboring metal components 3003. The reason for implementing metalislands 2908 between two power ground areas is that the metal islands2908 can at some degree prevent accidental short between two powerground areas that have two different voltage levels. The metal islands2908 are smaller in size compared with the metal components.

In some embodiments, the metal islands 2908 can be implementedsurrounding a signal trace. In some embodiment, the metal islands 2908can be implemented between two adjacent signal traces. In someembodiments, the metal islands 2908 can be implemented between a signaltrace and a power ground area. In some embodiments, the metal islands2908 can be implemented between a signal trace and another signal trace.

In some embodiments, the metal islands 2908 are electrically isolatedand are not connected to other power level or signal traces. A reasonfor implementing the metal islands around a signal trace is that itprovides certain degree of shielding and isolation effect so that thesignal trace being surrounded can have better signal integrity. Anotherreason for implementing the metal islands 2908 is to make the density ofmetal in the metal layer 2806 more uniform to get a better packagequality.

With reference to FIG. 31 , in some embodiments, the metal layer 2806comprises a power ground area 3101, a power ground area 3102, and apower ground area 3103. The power ground area 3101 has a plurality ofholes 3104. The width or diameter of most of the holes 3104 are greaterthan the width of metal traces 3105. The metal traces 3105 formboundaries and inner lines of each of the power ground areas. In someembodiments, the holes are not of the same size. For example, a hole3106 is twice the size of neighboring holes.

With reference to FIG. 19 , FIG. 20 , and FIG. 21 , according to anotherembodiment, a semiconductor device 1900 is disclosed. The semiconductordevice 1900 comprises a redistribution structure 1902, a die 1901, aDRAM module 1904, a printed circuit board 2101, and a non-volatilememory module 2102. The DRAM module 1904 is connected to theredistribution structure 1902 through solder bumps 1905 and conductiveposts 1903. The die 1901 is connected to the redistribution structure1902 through conductive pillars 2001. The redistribution structure 1902is connected to the printed circuit board 2101 through the solder bumps2006. The non-volatile memory module 2102 is connected to the printedcircuit board 2101 through solder bumps 2103.

In some embodiments, the semiconductor device 1900 comprises a DRAMmodule 1904, a die 1901, a redistribution structure 1902, a printedcircuit board 2101, and a non-volatile memory module 2102. The die 1901is located between the redistribution structure 1902 and the DRAM module1904. An area of the DRAM module 1904 is greater than an area of the die1901. An area of the redistribution structure is greater than an area ofthe DRAM module 1904. The redistribution structure 1902 is connected tothe printed circuit board 2101. The non-volatile memory module 2102 isconnected to the printed circuit board 2101. The redistributionstructure 1902 is electrically connected to the non-volatile memorymodule 2102 through the printed circuit board 2101.

With reference to FIG. 24 , the passivation layer 2401 can have singleor multiple layers of silicon nitride (Si3N4), silicon dioxide (SiO2),silicon oxynitride (SiON), SiO2/Si3N4, or other material havingdielectric properties. With reference to FIG. 20 and FIG. 28 , theinsulating layers 2002, 2801, 2802, 2803, and 2804 can be polyimide, BCB(Benzocyclobutene), PBO (PolyBenzobisOxazole), or other material havingsimilar insulating properties. With reference to FIG. 20 , the solderbump 2006 and the solder bumps 2006 include without limitation bothlead-based and lead-free solders, such as Pb—Sn compositions forlead-based solder, and lead-free solders including tin, copper, andsilver, or “SAC” compositions, and other eutectics that have a commonmelting point and form conductive solder connections in electricalapplications.

With reference to FIG. 20 , the conductive unit 2005 includes under bumpmetal (UBM). In some embodiments, UBM structures include one or moremetallic layers, such as layers of titanium and of copper. The UBM canbe formed by deposition. The conductive pillars 2001 can be aluminum(Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), orother suitable electrically conductive material. The molding material1918 can be a polymer composite material, such as epoxy resin withfiller, epoxy acrylate with filler, or polymer with proper filler. Withreference to FIG. 20 and FIG. 28 , the metal traces 2003, the vias 2004,the metal layers 2805, 2806, and 2807 can be aluminum (Al), copper (Cu),tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitableelectrically conductive material.

FIG. 33 shows a semiconductor package with a DRAM module. FIG. 34 showsa detailed redistribution structure. FIG. 35 shows an example of a metalpost. FIG. 36 shows another example of a metal post. FIG. 37 shows asolder bump at an end of a metal post. FIG. 38 shows a solder bump at anend of a metal post. FIG. 39 shows a semiconductor device.

According to an embodiment, with reference to FIG. 33 , FIG. 34 , andFIG. 36 , a semiconductor package 3300 comprises a redistributionstructure 3302, a processor die 3303, and a metal post 3307. A length ofthe metal post 3307 is greater than a thickness of the processor die3303. The metal post 3307 is placed beside the processor die 3303. Theprocessor die 3303 has an active side 3304 and a back side 3305. Theactive side 3304 faces a first direction 3306. The active side 3304 ofthe processor die 3303 is connected to the redistribution structure3302.

The metal post 3307 has a first end 3308, and a second end 3309. Themetal post 3307 is connected to the redistribution structure 3302 at thefirst end 3308. The first end 3308 faces the first direction 3306. Thefirst end 3308 has a first width 3502. The second end 3309 has a secondwidth 3503. The first width 3502 is greater than the second width 3503.The metal post 3307 has a side surface 3314. The side surface 3314 isinwardly curved.

The metal post 3307 can be formed by plating. The material for the metalpost 3307 can be Cu, Al, W, Au, solder, or other suitable electricallyconductive material. In some embodiments, the material in the metal post3307 is uniformed distributed. That is, the metal post 3307 does notinclude a non-uniform distribution of a mixture of two different metalmaterials. The processor die 3303 comprises at least a GPU (graphicsprocessing unit).

With reference to FIG. 36 , the structure of the metal post 3307 canprovide a wider connection areas at both ends. The process of formingelectrical connections at the ends of the metal post 3307 become easierbecause of the wider connection areas.

In some embodiments, with reference to FIG. 34 , the semiconductorpackage 3300 further comprises a set of metal vias 3406. The set ofmetal vias 3406 are connected between the active side 3304 of theprocessor die 3303 and the redistribution structure 3302. The method offorming the metal vias 3406 can be plating. The material of the metalvias 3406 can be copper or aluminum, or the like.

With reference to FIG. 37 , in some embodiments, the semiconductorpackage 3300 further comprises an insulating layer 3601 on a surface ofthe semiconductor package 3300. The insulating layer 3601 having atleast an opening 3602. The insulating layer 3601 has an outwardly curvedsurface 3605 around the opening 3602. The insulating layer 3601 can bepolyimide, BCB (Benzocyclobutene), PBO (PolyBenzobisOxazole), or othermaterial having similar insulating properties.

With reference to FIG. 37 , in some embodiments, the semiconductorpackage 3300 further comprises a solder bump 3603 located on the opening3602. In some embodiments, the insulating layer 3601 is a polyimidelayer. In some embodiments, with reference to FIG. 38 , the opening 3602has an opening width 3604. The opening width 3604 is smaller than thesecond width 3503 of the metal post 3307. In some embodiments, withreference to FIG. 33 , the semiconductor package 3300 further comprisesan adhesive layer 3311 located on the back side 3305 of the processordie 3303. The adhesive layer 3311 can be a die attach film (DAF), or thelike.

According to another embodiment, with reference to FIG. 33 , FIG. 34 ,and FIG. 36 , a semiconductor package 3300 comprises a redistributionstructure 3302, a processor die 3303, and a metal post 3307. The metalpost 3307 is placed beside the processor die 3303. A length of the metalpost 3307 is greater than a thickness of the processor die 3303. Theprocessor die 3303 has an active side 3304 and a back side 3305. Theactive side 3304 faces a first direction 3306. The active side 3304 ofthe processor die 3303 is connected to the redistribution structure3302.

The metal post 3307 has a first end 3308, a second end 3309 and a waist3310. The metal post 3307 is connected to the redistribution structure3302 at the first end 3308. The first end 3308 faces the first direction3306. The first end 3308 has a first width 3502. The second end 3309 hasa second width 3503. The waist 3310 has a waist width 3501. The firstwidth 3502 is greater than the waist width 3501. The second width 3503is greater than the waist width 3501. The metal post 3307 has a sidesurface 3314. The side surface 3314 is inwardly curved.

In some embodiments, with reference to FIG. 33 , the semiconductorpackage 3300 further comprises a molding material 3312 filled betweenthe processor die 3303 and the metal post 3307. The molding material3312 can be a polymer composite material, such as epoxy resin withfiller, epoxy acrylate with filler, or polymer with proper filler.

In some embodiments, no solder material is located between the processordie 3303 and the redistribution structure 3302. In some embodiments, animaginary plane 3313 parallel with the redistribution structure 3302 andacross a side surface of the processor die 3303 does not intercept witha solder material.

In some embodiments, with reference to FIG. 34 , the redistributionstructure 3302 further comprises a first sublayer 3401, a secondsublayer 3402, and a third sublayer 3403. In some embodiments, theredistribution structure 3302 further comprises a fourth sublayer 3404,and a fifth sublayer 3405. The material of the first sublayer 3401, thesecond sublayer 3402, the third sublayer 3403, the fourth sublayer 3404,and the fifth sublayer 3405 can be polyimide, BCB (Benzocyclobutene),PBO (PolyBenzobisOxazole), or other material having similar insulatingproperties.

In some embodiments, the semiconductor package 3300 further comprises aninsulating layer 3601 on a surface of the semiconductor package 3300.The insulating layer 3601 has at least an opening 3602. The insulatinglayer 3601 has an outwardly curved surface 3605 around the opening 3602.In some embodiments, the semiconductor package further comprises asolder bump 3603 located on the opening 3602.

According to another embodiment, with reference to FIG. 33 , thesemiconductor package 3300 comprises a redistribution structure 3302, aprocessor die 3303, and a metal post 3307. The metal post 3307 is placedbeside the processor die 3303. A length of the metal post 3307 isgreater than a thickness of the processor die 3303. The processor die3303 has an active side 3304 and a back side 3305. The active side 3304faces a first direction 3306. The active side 3304 of the processor die3303 is connected to the redistribution structure 3302.

With reference to FIG. 36 , the metal post 3307 has a first end 3308, asecond end 3309 and a waist 3310. The metal post 3307 is connected tothe redistribution structure 3302 at the first end 3308. The first end3308 faces the first direction 3306. The first end 3308 has a firstwidth 3502. The second end 3309 has a second width 3503. The waist 3310has a waist width 3501. The first width 3502 is greater than the secondwidth 3503. The second width 3503 is greater than the waist width 3501.The metal post 3307 has a side surface 3314. The side surface 3314 isinwardly curved.

In some embodiments, the semiconductor package 3300 further comprises amolding material 3312. The molding material 3312 surrounds the metalpost 3307. In some embodiments, the metal post 3307 is a copper post. Insome embodiments, the metal post 3307 is in direct contact with themolding material 3312 and no insulating layer is located between themolding material 3312 and the metal post 3307. The metal post 3307 doesnot go through a silicon substrate.

In some embodiments, with reference to FIG. 34 , the redistributionstructure 3302 further comprises a first sublayer 3401, a secondsublayer 3402, and a third sublayer 3403. In some embodiments, the firstsublayer 3401 comprises a set of first metal traces 3407. The secondsublayer 3402 comprises a set of second metal traces 3408. The thirdsublayer 3403 comprises a set of third metal traces 3409. In someembodiments, the redistribution structure 3302 further comprises afourth sublayer 3404 and a fifth sublayer 3405.

In some embodiments, the fourth sublayer 3404 comprises a set of fourthmetal traces 3410, and the fifth sublayer 3405 comprises a set of fifthmetal traces 3411. The material of the first traces 3407, the secondtraces 3408, the third traces 3409, the fourth traces 3410, and thefifth traces 3411 can be aluminum (Al), copper (Cu), tin (Sn), nickel(Ni), gold (Au), or silver (Ag), or other suitable electricallyconductive material.

In some embodiments, with reference to FIG. 34 , the semiconductorpackage 3300 further comprises a molding material 3412 filled betweenthe processor die 3303 and the first sublayer 3401. In some embodiments,the semiconductor package 3300 further comprises a set of metal vias3406 connected between the redistribution structure 3302 and theprocessor die 3303. In some embodiments, the processor die 3303 furthercomprises a set of metal pads 3413. The set of metal pads 3413 areconnected to the set of metal vias 3406.

According to an embodiment, with reference to FIG. 33 , FIG. 34 , FIG.36 , FIG. 37 , and FIG. 39 , a semiconductor device 700 comprises aredistribution structure 3302, a processor die 3303, a metal post 3307,a DRAM module 3315, a printed circuit board 3901, and a flash memory3902. The metal post 3307 is placed beside the processor die 3303. Alength of the metal post 3307 is greater than a thickness of theprocessor die 3303. The processor die 3303 has an active side 3304 and aback side 3305. The active side 3304 faces a first direction 3306. Theactive side 3304 of the processor die 3303 is connected to theredistribution structure 3302.

The metal post 3307 has a first end 3308, and a second end 3309. Themetal post 3307 is connected to the redistribution structure 3302 at thefirst end 3308. The first end 3308 faces the first direction 3306. Thefirst end 3308 has a first width 3502. The second end 3309 has a secondwidth 3503. The first width 3502 is greater than the second width 3503.The metal post 3307 has a side surface 3314. The side surface 3314 isinwardly curved.

The DRAM module 3315 is connected to the semiconductor package 3300through a set of first solder bumps 3603. The printed circuit board 3901is connected to the redistribution structure 3302 through a set ofsecond solder bumps 3904. The flash memory 3902 is connected to theprinted circuit board 3901 through a set of third solder bumps 3905.

In some embodiments, a first size of the first solder bump 3603 issmaller the a second size of the second solder bump 3904. In someembodiments, the first size of the first solder bump 3603 is smallerthan a third size of the third solder bump 3905.

The material of the first solder bump 3603, the second solder bump 3904,and the third solder bump 3905 can be any metal or electricallyconductive material, e.g., Sn, lead (Pb), Au, Ag, Cu, zinc (Zn),bismuthinite (Bi), and alloys thereof, with an optional flux material.For example, the solder material can be eutectic Sn/Pb, high-lead, orlead-free.

According to another embodiment, with reference to FIG. 33 , FIG. 34 ,and FIG. 35 , the semiconductor package 3300 comprises a redistributionstructure 3302, a processor die 3303, and a metal post 3307. Theprocessor die 3303 has an active side 3304 and a back side 3305. Theactive side 3304 faces a first direction 3306. The active side 3304 ofthe processor die 3303 is connected to the redistribution structure3302.

The metal post 3307 has a first end 3308, a second end 3309 and a waist3310. The metal post 3307 is connected to the redistribution structure3302 at the first end 3308. The first end 3308 faces the first direction3306. The first end 3308 has a first width 3502. The second end 3309 hasa second width 3503. The waist 3310 has a waist width 3501. The firstwidth 3502 is smaller than the waist width 3501. The second width 3503is smaller than the waist width 3501. The metal post 3307 has a sidesurface 3314. The side surface 3314 is outwardly curved.

With reference to FIG. 35 , in some embodiments, the material of themetal post 3307 can be a solder material. The space for placing thesolder material can be formed by laser drill or photolithography. Insome embodiments, the material of the metal post 3307 can be aluminum(Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), orother suitable electrically conductive material.

Some embodiments of the semiconductor package 3300 can provide a metalpost 3307 with wider connection areas at both ends. Some embodiments ofthe semiconductor package 3300 can provide a metal post 3307 capable ofconnecting to a DRAM module 3315 through a molding material 3312. Someembodiments of the semiconductor package 3300 can provide a metal post3307 with a wider connection area at an end connecting to aredistribution structure 3302.

FIG. 40 shows a semiconductor device. FIG. 41 shows a detailedredistribution structure. FIG. 42 shows a top view and a cross-sectionalview of a conductive via. FIG. 43 shows a top view and a cross-sectionalview of a conductive via. FIG. 44 shows cross-sectional views ofconductive vias. FIG. 45 shows cross-sectional views of conductive vias.FIG. 46 shows a top view of a conductive via. FIG. 47 shows a top viewof a conductive via. FIG. 48 shows a top view of a conductive via. FIG.49 shows a top view of a conductive via.

According to an embodiment, with reference to FIG. 42 , a conductive via4106 comprises a base 4201 and an annular flange 4203. The base 4201 iscup-shaped. The base 4201 has a rim 4202. The annular flange 4203 isconnected to the rim 4202 of the base 4201. The annular flange 4203 hasa first opening 4204.

In some embodiments, the conductive via 4106 further comprises a secondopening 4206. The first opening 4204 and the second opening 4206 aresymmetric with respect to a central point 4205 of the base 4201. In someembodiments, the conductive via 4106 is a copper via.

According to another embodiment, with reference to FIG. 41 , FIG. 42 ,and FIG. 43 , a redistribution structure 4100 comprises a first sublayer4101, and a second sublayer 4102. The first sublayer 4101 comprises afirst conductive via 4106.

The second sublayer 4102 is located on the first sublayer 4101. Thesecond sublayer 4102 comprises a second conductive via 4107. The secondconductive via 4107 is similar to the first conductive via 4106 in shapeand structure. The second conductive via 4107 comprises a base 4201 andan annular flange 4203. The base 4201 is cup-shaped. The base has a rim4202. The annular flange 4203 is connected to the rim 4202 of the base4201. The annular flange 4203 has at least an opening 4204.

In some embodiments, the first conductive via 4106 comprises a base 4201and an annular flange 4203. The base 4201 is cup-shaped. The base has arim 4202. The annular flange 4203 is connected to the rim 4202 of thebase 4201. The annular flange 4203 has at least an opening 4204.

In some embodiments, with reference to FIG. 41 and FIG. 42 , theredistribution structure 4100 further comprises a third sublayer 4103.The third sublayer 4103 comprises a third conductive via 4108. The thirdconductive via 4108 is similar to the first conductive via 4106, whichcomprises a base 4201 and an annular flange 4203. The base 4201 iscup-shaped. The base 4201 has a rim 4202. The annular flange 4203 isconnected to the rim 4202 of the base 4201. The annular flange 4203 hasat least an opening 4204.

With reference to FIG. 43 , the first opening 4204 has a first inneredge 4207. The second opening has a second inner edge 4208. The firstinner edge 4207 is along a first axis 4209. The second inner edge 4208is along a second axis 4210. The conductive via 4106 has an inner edgedistance 4211 between the first axis 4209 and the second axis 4210.

In some embodiments, with reference to FIG. 43 , FIG. 44 , and FIG. 45 ,the first conductive via 4106 has a first inner edge distance 4211. Thesecond conductive via 4107 has a second inner edge distance 4212. Thethird conductive via 4108 has a third inner edge distance 4213. In someembodiments, the first inner edge distance 4211 is smaller than thethird inner edge distance 4213.

In some embodiments, with reference to FIG. 41 and FIG. 42 , theredistribution structure 4100 further comprises a fourth sublayer 4104.The fourth sublayer 4104 comprises a fourth conductive via 4109. Thefourth conductive via 4109 is similar to the first conductive via 4106,which comprises a base 4201 and an annular flange 4203. The base 4201 iscup-shaped. The base 4201 has a rim 4202. The annular flange 4203 isconnected to the rim 4202 of the base 4201. The annular flange 4203 hasat least an opening 4204.

In some embodiments, with reference to FIG. 41 and FIG. 42 , theredistribution structure 4100 further comprises a fifth sublayer 4105.The fifth sublayer 4105 comprises a fifth conductive via 4110. The fifthconductive via 4110 is similar to the first conductive via 4106, whichcomprises a base 4201 and an annular flange 4203. The base 4201 iscup-shaped. The base 4201 has a rim 4202. The annular flange 4203 isconnected to the rim 4202 of the base 4201. The annular flange 4203 hasat least an opening 4204.

In some embodiments, with reference to FIG. 43 , FIG. 44 , and FIG. 45 ,the fourth conductive via 4109 has a fourth inner edge distance 4214.The fifth conductive via 4110 has a fifth inner edge distance 4215. Insome embodiments, the first inner edge distance 4211 is smaller than thesecond inner edge distance 4212. In some embodiments, the second inneredge distance 4212 is smaller than the third inner edge distance 4213.In some embodiments, the third inner edge distance 4213 is smaller thanthe fourth inner edge distance 4214. In some embodiments, the fourthinner edge distance 4214 is smaller than the fifth inner edge distance4215.

In some embodiments, with reference to FIG. 41 and FIG. 46 , at leastone of the first conductive 4106, the second conductive via 4107, thethird conductive via 4108, the fourth conductive via 4109, and the fifthconductive via 4110 is a conductive via 4600. The conductive via 4600has openings 4601. The openings 4601 are symmetric with respect to acentral point 4602.

In some embodiments, with reference to FIG. 41 and FIG. 47 , any one ofthe first conductive 4106, the second conductive via 4107, the thirdconductive via 4108, the fourth conductive via 4109, and the fifthconductive via 4110 can be a conductive via 4700. The conductive via4700 has openings 4701. The openings 4701 are symmetric with respect toa central point 4702. The openings 4702 are rectangular in shape.

In some embodiments, any one of the first conductive 4106, the secondconductive via 4107, the third conductive via 4108, the fourthconductive via 4109, and the fifth conductive via 4110 can be aconductive via 4800. The conductive via 4800 has openings 4801 andopenings 4803. The openings 4801 and openings 4803 are symmetric withrespect to a central point 4802. The openings 4803 are rectangular inshape. The openings 4801 are trapezoid in shape.

In some embodiments, with reference to FIG. 41 and FIG. 49 , any one ofthe first conductive 4106, the second conductive via 4107, the thirdconductive via 4108, the fourth conductive via 4109, and the fifthconductive via 4110 can be a conductive via 4900. The conductive via4900 has openings 4901 and openings 4903. The openings 4901 and openings4903 are symmetric with respect to a central point 4902. The openings4903 are rectangular in shape.

According to another embodiment, with reference to FIG. 40 , FIG. 41 ,FIG. 42 , and FIG. 46 , a semiconductor device 4000 comprises a die4001, a redistribution structure 4100, a metal post 4007, and a memorymodule 4010. The die 4001 has an active side 4003 and a back side 4004.

The redistribution structure 4100 has a front side 4005 and a back side4006. The front side 4005 of the redistribution structure 4100 isconnected to the active side 4003 of the die 4001 through a set of metalpillars 4301. The redistribution structure 4100 comprises a conductivevia 4600. The conductive via 4600 has at least an opening 4601.

The metal post 4007 has a first end 4008 and a second end 4009. Themetal post 4007 is connected to the front side 4005 of theredistribution structure 4100 at the first end 4008. The memory module4010 is connected to the metal post 4007 through a solder bump 4011.

In some embodiments, with reference to FIG. 47 , FIG. 48 , and FIG. 49 ,the redistribution structure 4100 comprises a conductive via 4700. Theconductive via 4700 has at least an opening 4701. In some embodiments,the redistribution structure 4100 comprises a conductive via 4800. Theconductive via 4800 has at least an opening 4801. In some embodiments,the redistribution structure 4100 comprises a conductive via 4900. Theconductive via 4900 has at least an opening 4901.

In some embodiments, with reference to FIG. 49 , the opening 4901 has aninner end 4904 and an outer end 4905. The inner end 4904 has a firstcurvature. The outer end 4905 has a second curvature. The firstcurvature is larger than the second curvature.

In some embodiments, the opening 4801 has a trapezoid shape. The opening4801 has an inner side 4804 and an outer side 4805. The inner side 4804has a first width. The outer side 4805 has a second width. The firstwidth is smaller than the second width.

In some embodiments, with reference to FIG. 41 and FIG. 46 , theredistribution structure 4100 comprises a first sublayer 4101. Theconductive via 4600 is formed in the first sublayer 4101. In someembodiments, the first sublayer 4101 comprises a polyimide and thepolyimide fills the opening 4601. In some embodiments, theredistribution structure 4100 further comprises a second sublayer 4102.The conductive via 4600 is formed in the second sublayer 4102.

In some embodiments, the second sublayer 4102 comprises a polyimide andthe polyimide fills the opening 4601. In some embodiments, theredistribution structure 4100 further comprises a third sublayer 4103.The conductive via 4600 is formed in the third sublayer 4103. In someembodiments, the third sublayer 4103 comprises a polyimide and thepolyimide fills the opening 4601.

In some embodiments, the redistribution structure 4100 further comprisesa fourth sublayer 4104. The conductive via 4600 is formed in the fourthsublayer 4104. In some embodiments, the fourth sublayer 4104 comprises apolyimide and the polyimide fills the opening 4601. In some embodiments,the redistribution structure 4100 further comprises a fifth sublayer4105. The conductive via 4600 is formed in the fifth sublayer 4105.

In some embodiments, the fifth sublayer 4105 comprises a polyimide andthe polyimide fills the opening 4601. In some embodiments, thesemiconductor device 4000 further comprises an adhesive layer 4012located on the back side 4004 of the die 4001. In some embodiments, thesemiconductor device 4000 further comprises a molding material 4013filled between the metal post 4007 and the die 4001.

With reference to FIG. 46 , FIG. 47 , FIG. 48 , FIG. 49 , and FIG. 50 ,any one of the openings 4601, 4701, 4801, 4803, 4901, 4903, and 5001 canbe implemented in any one of the first conductive via 4106, the secondconductive via 4107, the third conductive via 4108, the fourthconductive via 4109, and the fifth conductive via 4110.

The material of the first sublayer 4101, the second sublayer 4102, thethird sublayer 4103, the fourth sublayer 4004, and the fifth sublayer4005 can be polyimide, BCB (Benzocyclobutene), PBO(PolyBenzobisOxazole), or other material having similar insulatingproperties.

The material of the first conductive via 4106, the second conductive via4107, the third conductive via 4108, the fourth conductive via 4109, andthe fifth conductive via 4110 can be aluminum (Al), copper (Cu), tin(Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitableelectrically conductive material.

The metal post 4007 can be formed by plating. The material for the metalpost 4007 can be Cu, Al, W, Au, solder, or other suitable electricallyconductive material. In some embodiments, the material in the metal post4007 is uniformed distributed. That is, the metal post 4007 does notinclude a non-uniform distribution of a mixture of two different metalmaterials.

The first conductive via 4106, the second conductive via 4107, the thirdconductive via 4108, the fourth conductive via 4109, and the fifthconductive via 4110 can be formed by plating. The material for theplating can be Cu, Al, W, Au, solder, or other suitable electricallyconductive material.

In some embodiments, any one of the first sublayer 4101, the secondsublayer 4102, the third sublayer 4103, the fourth sublayer 4104, andthe fifth sublayer 4105 can comprise a conductive via 4700. Theconductive via 4700 has openings 4701. The openings 4701 are symmetricwith respect to a central point 4702. The openings 4701 are rectangularin shape. A polyimide fills in the openings 4701. In some embodiments,the polyimide can be replaced by BCB (Benzocyclobutene), PBO(PolyBenzobisOxazole), or other material having similar insulatingproperties.

In some embodiments, any one of the first sublayer 4101, the secondsublayer 4102, the third sublayer 4103, the fourth sublayer 4104, andthe fifth sublayer 4105 can comprise a conductive via 4800. Theconductive via 4800 has openings 4801 and openings 4803. The openings4801 and openings 4803 are symmetric with respect to a central point4802. A polyimide fills in the openings 4801 and openings 4803. In someembodiments, the polyimide can be replaced by BCB (Benzocyclobutene),PBO (PolyBenzobisOxazole), or other material having similar insulatingproperties.

In some embodiments, any one of the first sublayer 4101, the secondsublayer 4102, the third sublayer 4103, the fourth sublayer 4104, andthe fifth sublayer 4105 can comprise a conductive via 4900. Theconductive via 4900 has openings 4901 and openings 4903. The openings4901 and openings 4903 are symmetric with respect to a central point4902. A polyimide fills in the openings 4901 and openings 4903. In someembodiments, the polyimide can be replaced by BCB (Benzocyclobutene),PBO (PolyBenzobisOxazole), or other material having similar insulatingproperties.

In some embodiments, with reference to FIG. 50 , any one of the firstconductive via 4106, the second conductive via 4107, the thirdconductive via 4108, the fourth conductive via 4109, and the fifthconductive via 4110 can be a conductive via 5000. The conductive via5000 has openings 5001. The openings 5001 are symmetric with respect toan axis 5002. The openings 5001 are arc segments in shape.

In some embodiments, with reference to FIG. 42 , the conductive via 4106comprises a base 4201 and an annular flange 4203. The base 4201 iscup-shaped. The base 4201 has a rim 4202, a slanting wall 4216, and abottom side 4217. The annular flange 4203 is connected to the rim 4202of the base 4201. The annular flange 4203 has a first opening 4204. Insome embodiments, a first thickness of the annular flange 4203 issubstantially the same as a second thickness of the bottom side 4217.

In some embodiments, with reference to FIG. 44 and FIG. 45 , theconductive via 4107, the conductive via 4108, the conductive via 4109,and the conductive via 4110 have a structure similar to that of theconductive via 4106. The conductive via 4107 has a slanting wall 4218and a bottom side 4219. The conductive via 4108 has a slanting wall 4220and a bottom side 4221. The conductive via 4109 has a slanting wall 4222and a bottom side 4223. The conductive via 4110 has a slanting wall 4224and a bottom side 4225.

In some embodiments, with reference to FIG. 41 and FIG. 44 , an innerportion 4226 of the cup-shaped conductive via 4106 is filled with aninsulating material. The insulating material can be a polyimide.

In some embodiments, with reference to FIG. 42 , a stress may exist onthe bottom side 4217. The source of the stress can be from the flange4203 and the slanting wall 4216. The stress can be released by theimplementation of the openings 4204 and 4206. Stress-induced voiding canalso be avoided by the openings. Similarly, with reference to FIG. 46 ,FIG. 47 , FIG. 48 , FIG. 49 , and FIG. 50 , the openings 4601, 4701,4801, 4803, 4901, 4903, and 5001 can release stresses coming fromcorresponding flanges and slanting side walls. The openings 4601, 4701,4801, 4803, 4901, 4903, and 5001 can avoid stress-induced voiding.

What is claimed is:
 1. An electronic device, comprising: aredistribution structure, the redistribution structure having a frontsurface and a back surface, the redistribution structure comprising aset of metal layers and a set of insulating layers, at least a middlemetal layer of the set of metal layers comprising a plurality of holes,at least a subset of the plurality of holes forming a mesh type area, atleast a width of one of the plurality of holes being greater than awidth of an inner line of the mesh type area; a processor die, theprocessor die having a front side and a back side, the front side of theprocessor die being connected to the front surface of the redistributionstructure; a set of conductive posts, the set of conductive posts beingplaced beside the processor die, the set of conductive posts beingconnected to the front surface of the redistribution structure, at leastone of the set of conductive posts having an inwardly curved sidesurface; a molding material disposed between the processor die and theset of conductive posts; a first set of solder bumps, the first set ofsolder bumps being connected to the set of conductive posts; a secondset of solder bumps, the second set of solder bumps being connected tothe back surface of the redistribution structure; and an underfillmaterial, the underfill material surrounding the first set of solderbumps; wherein a recess is formed between the redistribution structureand the processor die, and the recess is filled with the moldingmaterial.
 2. The electronic device of claim 1, further comprising acapacitor, the capacitor being connected to the back surface of theredistribution structure, the capacitor being within a verticalprojection of the processor die.
 3. The electronic device of claim 1,wherein the electronic device further comprises a DRAM module, the setof conductive posts are connected to the DRAM module through the firstset of solder bumps, and an area of the DRAM module is smaller than anarea of the redistribution structure from a top view.
 4. The electronicdevice of claim 1, wherein the electronic device further comprises: aDRAM module, the DRAM module being connected to the first set of solderbumps; a printed circuit board, the printed circuit board beingconnected to the back surface of the redistribution structure throughthe second set of solder bumps; a third set of solder bumps; and a flashmemory, the flash memory being connected to the printed circuit boardthrough the third set of solder bumps.
 5. The electronic device of claim4, further comprising metal pillars, the processor die being connectedto the redistribution structure through the metal pillars, the metalpillars comprising copper.
 6. The electronic device of claim 4, whereinat least one of the insulating layers comprises polyimide.
 7. Theelectronic device of claim 4, wherein an area of the DRAM module issmaller than an area of the redistribution structure from a top view. 8.An electronic device, comprising: a redistribution structure, theredistribution structure having a front surface and a back surface, theredistribution structure comprising a set of metal layers and a set ofinsulating layers; a plurality of metal pillars; a processor die, theprocessor die having a front side and a back side, the front side of theprocessor die being connected to the front surface of the redistributionstructure through the plurality of metal pillars; a set of conductiveposts, the set of conductive posts being placed beside the processordie, at least one of the set of conductive posts having an inwardlycurved side surface; a molding material disposed between the processordie and the set of conductive posts; a first set of solder bumps, thefirst set of solder bumps being connected to the set of conductiveposts, the first set of solder bumps having a first size; a DRAM module,the DRAM module being connected to the first set of solder bumps; asecond set of solder bumps, the second set of solder bumps having asecond size; a printed circuit board, the printed circuit board beingconnected to the back surface of the redistribution structure throughthe second set of solder bumps; a third set of solder bumps, the thirdset of solder bumps having a third size; and a flash memory, the flashmemory being connected to the printed circuit board through the thirdset of solder bumps; wherein the first size is smaller than the thirdsize.
 9. The electronic device of claim 8, further comprising acapacitor located on the back surface of the redistribution structure.10. The electronic device of claim 9, wherein the set of metal layerscomprises a first metal layer and a second metal layer, the set ofinsulating layers comprises a first insulating layer, a secondinsulating layer, and a third insulating layer, the first insulatinglayer is located on the back surface of the redistribution structure,the first metal layer is located adjacent to the first insulating layer,the second insulating layer is located adjacent to the first metallayer, the second metal layer is located adjacent to the secondinsulating layer, the third insulating layer is located adjacent to thesecond metal layer, and the electronic device further comprises: aconductive unit, the conductive unit being located on the back surfaceof the redistribution structure, the conductive unit being directlyconnected to at least one of the second set of solder bumps; a firstconductive via located in the second insulating layers; and a secondconductive via located in the third insulating layer; wherein the secondconductive via is closer to a central point of the conductive unit thanthe first conductive via from a top view.
 11. The electronic device ofclaim 9, wherein the set of metal layers comprises a first metal layerand a second metal layer, the set of insulating layers comprises a firstinsulating layer, a second insulating layer, and a third insulatinglayer, the first insulating layer is located on the back surface of theredistribution structure, the first metal layer is located adjacent tothe first insulating layer, the second insulating layer is locatedadjacent to the first metal layer, the second metal layer is locatedadjacent to the second insulating layer, the third insulating layer islocated adjacent to the second metal layer, and the electronic devicefurther comprises: a conductive unit, the conductive unit being locatedon the back surface of the redistribution structure, the conductive unitbeing directly connected to at least one of the second set of solderbumps; a first conductive via located in the second insulating layer; asecond conductive via located in the second insulating layer; a thirdconductive via located in the second insulating layer, the firstconductive via and the conductive third via being symmetric with respectto a central point; and a fourth conductive via located in the secondinsulating layer, the second conductive via and the fourth conductivevia being symmetric with respect to the central point.
 12. Theelectronic device of claim 9, wherein the set of metal layers comprisesa first metal layer and a second metal layer, the set of insulatinglayers comprises a first insulating layer, a second insulating layer,and a third insulating layer, the first insulating layer is located onthe back surface of the redistribution structure, the first metal layeris located adjacent to the first insulating layer, the second insulatinglayer is located adjacent to the first metal layer, the second metallayer is located adjacent to the second insulating layer, the thirdinsulating layer is located adjacent to the second metal layer, and theelectronic device further comprises: a conductive unit, the conductiveunit being located on the back surface of the redistribution structure,the conductive unit being directly connected to at least one of thesecond set of solder bumps; a first conductive via located in the secondinsulating layer; a second conductive via located in the secondinsulating layer; and a third conductive via located in the thirdinsulating layer, the third conductive via being closer to a centralpoint of the conductive unit than the first conductive via from a topview.
 13. The electronic device of claim 9, further comprising a polymerlayer, the polymer layer being located on the front side of theprocessor die, wherein a recess is formed between the redistributionstructure and the processor die, there is a horizontal shift between adie edge of the processor die and an outer edge of the polymer layer,and the recess is filled with the molding material.
 14. The electronicdevice of claim 9, wherein the set of metal layers comprises a firstmetal layer and a second metal layer, the set of insulating layerscomprises a first insulating layer, a second insulating layer, and athird insulating layer, the first insulating layer is located on theback surface of the redistribution structure, the first metal layer islocated adjacent to the first insulating layer, the second insulatinglayer is located adjacent to the first metal layer, the second metallayer is located adjacent to the second insulating layer, the thirdinsulating layer is located adjacent to the second metal layer, and theelectronic device further comprises: a conductive unit, the conductiveunit being located on the back surface of the redistribution structure,the conductive unit being directly connected to at least one of thesecond set of solder bumps; a first set of conductive vias located inthe second insulating layers; and a second set of conductive viaslocated in the third insulating layer, wherein the second set ofconductive vias are closer to a central point of the conductive unitthan the first set of conductive vias from a top view; wherein theplurality of metal pillars comprises copper.
 15. An electronic device,comprising: a redistribution structure, the redistribution structurehaving a front surface and a back surface, the redistribution structurecomprising a first metal layer and a second metal layer, theredistribution structure comprising a first insulating layer, a secondinsulating layer, and a third insulating layer, the first insulatinglayer being located on the back surface of the redistribution structure,the first metal layer being located adjacent to the first insulatinglayer, the second insulating layer being located adjacent to the firstmetal layer, the second metal layer being located adjacent to the secondinsulating layer, the third insulating layer being located adjacent tothe second metal layer, the second metal layer having a plurality ofholes; a processor die, the processor die having a front side and a backside, the front side of the processor being connected to the frontsurface of the redistribution structure; a first set of solder bumps,the first set of solder bumps having a first size; a second set ofsolder bumps, the second solder bumps having a second size; a third setof solder bumps, the third set of solder bumps having a third size,wherein the first size is smaller than the third size; a conductiveunit, the conductive unit being located on the back surface of theredistribution structure, the conductive unit being directly connectedto at least one of the second set of solder bumps; a first conductivevia located in the second insulating layer; a second conductive vialocated in the second insulating layer; a third conductive via locatedin the third insulating layer, the third conductive via being closer toa central point of the conductive unit than the first conductive viafrom a top view; a conductive post, the conductive post having a firstend and a second end, the first end having a first end width, the secondend having a second end width, the conductive post having a curved sidesurface, the conductive post being connected to the front surface of theredistribution structure at the first end, the conductive post beingconnected to one of the first set of solder bumps at the second end; aprinted circuit board, wherein the redistribution structure is connectedto the printed circuit board through the second set of solder bumps; anda flash memory, the flash memory being connected to the printed circuitboard through the third set of solder bumps.
 16. The electronic deviceof claim 15, wherein the curved side surface is an inwardly curved sidesurface.
 17. The electronic device of claim 15, wherein the curved sidesurface is an outwardly curved side surface.
 18. The electronic deviceof claim 15, further comprising a capacitor and a DRAM module, thecapacitor being located on the back surface of the redistributionstructure, the capacitor being within a vertical projection of theprocessor die, the DRAM module being connected to the first set ofsolder bumps, wherein an area of the DRAM module is smaller than an areaof the redistribution structure.